The present invention relates to a delay circuit and method thereof, and particularly relates to a delay circuit that can detect if the delay stages have delay faults or not, and a related method.
FIG. 1 illustrates a circuit diagram of a related art delay circuit 100. The delay circuit 100 includes a plurality of delay stages 101, 103, 105 . . . 10n (only part of the delay stages are illustrated), and utilizes a selection signal SS to select a number of delay stages to delay the input data signal Datain by a desired delay amount in order to generate a desired output data signal Dataout. One or more of the delay stages may have a delay fault, however, causing erroneous generation of the output data signal. Therefore, detection methods to detect if a delay circuit has delay faults or not are developed.
One example of a detection method is inputting an input clock signal to a path having a specific number of delay stages of a delay circuit and checking if the output clock signal changes corresponding to the value of the input clock signal. If yes, the delay circuit is fine, if not, at least one delay stage on the path has a delay fault, thus the delay circuit should be abandoned.
There may be a delay time between the changing of the input clock value to the output clock signal. Such a delay time is acceptable if it is smaller than a specific value, so another detection method inputs two clock signals having a minor time difference to a path having a specific number of delay stages of a delay circuit and checking if the output signal changes in the acceptable delay time. If yes, the delay circuit is fine, if not, at least one delay stage on the path has a delay fault, and the delay circuit should therefore be abandoned.
Such a mechanism has various disadvantages, however. For example, if there is a delay time between the changing of the input clock value to the output clock signal, a flip flop is needed to detect if the delay circuit has a delay fault or not, but a delay circuit does not initially include a flip flop. Additionally, a delay stage may have an acceptable delay amount variance, but the delay amount variance may affect the determination result, since it is difficult to distinguish whether said delay amount variance is the acceptable delay amount or the unacceptable time delay.